1、题目Consider the state diagram shown below.Write complete Verilog code that represents this FSM. Use separatealwaysblocks for the state table and the state flip-flops, as done in lectures. Describe the FSM output, which is calledz, using either continuous assignment statement(s) or analwaysblock (at your discretion). Assign any state codes that you wish to use.2、代码和上一个基本一样只是w变成了~wmodule top_module ( input clk, input reset, // Synchronous active-high reset input w, output z ); parameter A6b000001,B6b000010,C6b000100,D6b001000,E6b010000,F6b100000; reg [6:1]state,next_state; always(posedge clk) if(reset) stateA; else statenext_state; assign next_state[1]state[1](~w)||state[4](~w); assign next_state[2]state[1]w; assign next_state[3]state[2]w||state[6]w; assign next_state[4]state[2](~w)||state[3](~w)||state[5](~w)||state[6](~w); assign next_state[5]state[3]w||state[5]w; assign next_state[6]state[4]w; assign zstate[5]||state[6]; endmodule